Solid-state imaging device and driving method thereof, and electronic apparatus using the same

ABSTRACT

Provided is a solid-state imaging device including: a pixel array section that pixels which detect a physical quantities are arranged in two dimensions of matrix; an AD converting section that performs AD (Analog-Digital) conversion for a plurality of channels of analog pixel signals which are read-out from the pixel array section; and a control section that sets quantized units AD-converted by the AD conversion section according to a gain setting of the unit pixel signal, wherein the control section determines the grayscale number of digital outputs AD-converted for at least one channel of the unit pixel signals according to the gain setting of the pixel signal.

BACKGROUND

The present disclosure relates to a solid-state imaging device and adriving method thereof, and an electronic apparatus using the same, andparticularly, related to a solid-state imaging device and a drivingmethod thereof, and an electronic apparatus using the same, which areobtainable a plurality of signals having different sensitivities toexpand a dynamic range thereof.

In the related art, as a method of expanding the dynamic range of asignal amount output corresponding to an incident light amount to asolid-state imaging device, there is a method that reads-out a samepixel several times with a plurality of different exposure times andthen combines the read-out signals having different sensitivities fromeach other at the followed stage (for example, refer to Japanese PatentNo. 3680366 and Orly Yadid-Pecht and Eric R. Fossum, “Wide IntrasceneDynamic Range CMOS APS Using Dual Sampling”, IEEE TRANSACTIONS ONELECTRON DEVICES, VOL. 44, NO. 10, pp. 1721-1723, OCTOBER 1997.).

SUMMARY

In the method above, the information of a low illuminance portion can beobtained from a long exposure time of signal and the information of thehigh illuminance portion can be obtained from a short exposure time ofsignal. However, when a subject is in the low illuminance, it isnecessary at least to extend the exposure time of the signal with thelong exposure time, but there is a limitation in extending of theexposure time of the signal with the long exposure time. For example, inthe dynamic image, the maximum exposure time is only 1/30 sec. Also, ina still image, in order to inhibit a biasing of hand or subject, it hasbeen desirably avoided to extend the exposure time over a predeterminedtime.

In this case, even in the signal with the long exposure time, since asignal amount is small, it is necessary to raise the gain setting of thesolid-state imaging device. To raise the gain setting, there are twomethods, that is, one raising an analog gain before an AD (Analog toDigital) conversion, and the other raising the digital gain after the ADconversion.

In the method raising a digital gain, raising the digital gain causes acoarse grayscale of an image. Also, in the method raising the analoggain, in a case where a portion of an image surface is bright, a signalof the bright portion exceeds the input range of the AD conversioncircuit carrying out AD conversion, and thus in spite of originallyexisting of an signal, the signal is lost. Of course, the signal of thebright portion is able to obtain from the signal of the short exposuretime, but when compared with the signal of the long exposure time, S/N(Signal/Noise) is low and thus, there has been a concern that the S/N ofthe obtained image decreases.

The present disclosure has been derived in view of this circumstance andaccordingly, even when raising the analog gain in order to obtain aplurality of signals having different sensitivities and then expand adynamic range thereof, it is desirable that the loss of information ofconnecting portions of a high sensitivity signal and a low sensitivitysignal is prevented, thereby it is able to obtain signals having a highS/N.

According to an embodiment of the present disclosure, there is provideda solid-state imaging device including a pixel array section that pixelswhich detect physical quantities are arranged in two dimensions ofmatrix, an AD converting section that performs AD (Analog-Digital)conversion for a plurality of channels of analog pixel signals which areread-out from the unit pixel array section, and a control section thatsets quantized units AD-converted by the AD conversion section accordingto a gain setting of the unit pixel signal, wherein the control sectiondetermines grayscale numbers of digital outputs AD-converted for atleast one channel of the unit pixel signals according to the gainsetting of the pixel signal.

When raising the gain of the unit pixel signal, the control sectioncontrols the quantized unit AD-converted by the AD conversion section tobe small and the grayscale number of the digital output AD-converted forthe unit pixel signal of at least one channel at the same time to belarge.

In the solid-state imaging device according to the embodiment of thepresent disclosure, the AD conversion section performs AD conversion bythe AD conversion section for pixel signals of the plurality of channelswhich sensitivities are different from each other, and when raising thegain of the unit pixel signal, the control section controls thequantized unit AD-converted by the AD conversion section to be small andthe grayscale number of the digital output AD-converted for the unitpixel signals, of which sensitivities are high, of at least one channelto be large.

In the solid-state imaging device according to the embodiment of thepresent disclosure, when raising the gain of the unit pixel signal, thecontrol section controls the grayscale number of the digital outputAD-converted for the unit pixel signal, of which the sensitivity is low,of at least one channel not to change.

In the solid-state imaging device according to the embodiment of thepresent disclosure, before raising the gain of the unit pixel signal,the control section controls the grayscale number of the digital outputAD-converted for the unit pixel signal, of which the sensitivity ishigh, of at least one channel to lower than the value of the grayscalenumber of the digital output AD-converted for the unit pixel signal, ofwhich the sensitivity is low, of at least one channel.

In the solid-state imaging device according to the embodiment of thepresent disclosure, the AD conversion section performs AD conversion forpixel signals, which the sensitivity are different from each other, ofthe plurality of channels by setting differently a detecting time fordetecting the physical quantity of the unit pixel.

According to another embodiment of the present disclosure, there isprovided a method for driving of a solid-state imaging device whichincludes a pixel array section that pixels which detect a physicalquantity are arranged in two dimensions of matrix, an AD convertingsection that performs AD (Analog-Digital) conversion for a plurality ofchannels of analog pixel signals which are read-out from the unit pixelarray section, a control section that sets quantized units AD-convertedby the AD conversion section according to a gain setting of the unitpixel signal, wherein the method including step of determining agrayscale number of the digital output AD-converted for at least onechannel of the unit pixel signals according to the gain setting of thepixel signal.

According to still another embodiment of the present disclosure, thereis provided an electronic apparatus which is provided with a solid-stateimaging device, wherein the solid-state imaging device including a pixelarray section that pixels which detect physical quantities are arrangedin two dimensions of matrix, an AD converting section that performs AD(Analog-Digital) conversion for a plurality of channels of analog pixelsignals which are read-out from the unit pixel array section, and acontrol section that sets quantized units AD-converted by the ADconversion section according to a gain setting of the unit pixel signal,wherein the control section determines grayscale numbers of digitaloutputs AD-converted for at least one channel of the unit pixel signalsaccording to the gain setting of the pixel signal.

According to the embodiments of the present disclosure, AD conversionfor a plurality of channels of analog pixel signals read-out from apixel array section is performed and quantized units AD-converted by theAD conversion section according to gain setting of pixel signals areset, and the grayscale number of the AD-converted digital output forpixel signals of at least one channel according to gain setting of pixelsignals is determined.

According to the embodiments of the present disclosure, it is possibleto prevent the loss of information as well as to obtain a high S/N ofimage in a case of obtaining a plurality of signals having differentsensitivities and expanding a dynamic range thereof, when raising ananalog gain.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example of configuration accordingto an embodiment of a solid-state imaging device that the presentdisclosure is adopted.

FIG. 2 is a diagram illustrating an example of a configuration ofcircuit for a unit pixel.

FIG. 3 is a diagram illustrating a shutter scan and a read-out scan oftwo channels to obtain signals having different sensitivities.

FIG. 4 is a block diagram illustrating an example of a configuration ofa column signal processing circuit.

FIG. 5 is a diagram illustrating a dynamic range of a low illuminancesignal and a high illuminance signal to an incident light amount.

FIG. 6 is a diagram illustrating a coefficient using for combining ofthe low illuminance signal and the high illuminance signal.

FIG. 7 is a diagram illustrating a relationship of an analog gain withan input gain of an AD conversion circuit.

FIG. 8 is a diagram illustrating a relationship of the analog gain withthe input gain of an AD conversion circuit.

FIG. 9 is a diagram illustrating a relationship of the analog gain witha grayscale number of an AD conversion circuit.

FIG. 10 is a diagram illustrating a relationship analog gain with agrayscale number of an AD conversion circuit.

FIG. 11 is a diagram illustrating a relationship analog gain with agrayscale number of an AD conversion circuit.

FIG. 12 is a flow chart illustrating of a signal output process.

FIG. 13 is a flow chart illustrating of a signal output process.

FIG. 14 is a diagram illustrating an example of a configuration of anembodiment of an electronic apparatus adapted to the present disclosure.

FIG. 15 is a flow chart illustrating for a gain setting process.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments according to the present disclosure aredisclosed with reference to the attached drawings.

Configuration of Solid-State Imaging Device

FIG. 1 is illustrating a configuration of a solid-state imaging deviceaccording to an embodiment of the present disclosure. In thisembodiment, it discloses that an example of the solid-state imagingdevice is a CMOS (Complementary Metal Oxide Semiconductor) image sensor,which detects a physical quantity of electrical charge amountcorresponding to light amount of visible light as a unit of pixel.

As illustrated on FIG. 1, the CMOS image sensor 10 may be provided witha pixel array section 12 in which a unit pixel 11 (hereinafter, shortlyreferred to pixel 11) including photoelectric conversion device(s)converting the light amount of an incident visible light into aphotoelectric signal is arranged in rows and columns (matrix shape).

The CMOS image sensor 10 may be adapted to a pixel array section 12 andis provided with a control circuit 13 controlling the CMOS image sensor10 entirely, a vertical driving circuit 14 driving each pixel 11 of theunit pixel array section 12, n-channel(s) of column signal processingcircuits 15, 16 processing a signal output from each pixel 11,horizontal driving circuits 17, 18, horizontal signal lines 19, 20 andoutput circuits 21, 22.

Specifically, the CMOS image sensor 10 is a system of such aconfiguration that two channels of signal processing mechanism includinga column signal processing circuit 15, a horizontal driving circuit 17,a horizontal signal line 19, and an output circuit 21 and a columnsignal processing circuit 16, a horizontal driving circuit 18, ahorizontal signal line 20, and an output circuit 22 are arranged in bothsides above and below of the unit pixel array section 12.

In this configuration of the system, the control circuit 13 receivesdata for commanding an operation mode of the CMOS image sensor 10 or thelike from the outside and outputs data including information of the CMOSimage sensor 10 to the outside.

Further, on the basis of a vertical synchronized signal Vsync,horizontal synchronized signal Hsync and master clock MCK, the controlcircuit 13 generates such as clock signals or control signals whichplays as reference signals by which drive the vertical driving circuit14, the column signal processing circuit 15, 16, the horizontal drivingcircuit 17, 18 and the like. The clock signal or control signal, or thelike which is generated from the control circuit 13 is given to thevertical driving circuit 14, the column signal processing circuit 15,16, the horizontal driving circuit 17, 18 and the like.

In the pixel array section 12, unit pixels 11 are arranged in twodimensions of matrix. As illustrated on FIG. 1, the unit pixels 11 arearranged in tandem in a substantially square lattice. This means that anoptical opening which is prescribed by photoelectric conversion devicesor metal wires or the like is arranged in tandem in a substantiallysquare lattice, and the circuit portion of the unit pixel 11 is notlimited to this configuration. Namely, in the circuit portion of theunit pixel 11 as described below, there is no desired to be surelyarranged in parallel in a substantially square lattice.

Additionally, in the pixel array section 12, a pixel driving wire 23 pera pixel row is formed along with left and right directions (arraydirections of pixels in a pixel row) of the Figure and a vertical signalline 24 per a pixel column is formed along with upper and lowerdirections (array directions of pixels in a pixel column) of the Figurefor the unit pixel 11 arrangement of rows and columns. An end of thispixel driving wire 23 is connected to an output end corresponding toeach pixel row of the vertical driving circuit 14.

The vertical driving circuit 14 may be constituted by shift registers oraddress decoders, and selects and scans each pixel of the pixel arraysection 12 in a row unit subsequently, and then supplies a desireddriving pulse (control pulse) via the unit pixel driving wire 23 to eachpixel of the selected row.

Though a specific constitution of the vertical driving circuit 14 isomitted, it may be constituted to provide with a scan channel carryingout the read-out to scan selectively and subsequently pixels 11 in a rowunit, and a scan channel carrying out a sweeping scan by preceding moreas a shutter speed time portion than the reading-out scanning to sweepout (reset) undesirable electrical charges from the photoelectricconversion device read-out the unit pixel 11.

By sweeping out (reset) the undesirable electrical charges through thesweeping scan channel, so called the electronic shutter operation iscarried out. Hereinafter, it is called that the sweeping scan channel isan electronic shutter scan channel. Herein, so called the electronicshutter operation refers to operation which wastes light electricalcharges of the photoelectric conversion device, and then commences a newexposure (light electrical charge storage is commenced).

The read-out signal by the read-out operation through the read-out scanchannel corresponds to a light amount received just before the previousread-out operation or after the electron shutter operation. Also, aperiod from a read-out timing by just the previous read-out operationand a sweep-out timing by the electronic shutter operation to theread-out timing by a current read-out operation plays as a storage time(exposure time) of light electrical charges in a unit pixel 11.

Output signals from each pixel 11 of the selected row are supplied tothe column signal processing circuit 15 or the column signal processingcircuit 16 via the vertical signal line 24 respectively. The columnsignal processing circuits 15, 16 are respectively arranged above andbelow the unit pixel array section 12 with a corresponding relationshipof 1:1 per a pixel column, for example, of the pixel array section 12,that is, for the unit pixel column.

This column signal processing circuits 15, 16 receive output signalsfrom the selected rows per every pixel 11 row of the pixel array section12 and carry out a CDS (Correlated Double Sampling) process foreliminating a fixed pattern noise inherent in the signals, a signalamplifying process or the AD conversion process, or the like.

Also, herein, though a case that a configuration in which the columnsignal processing circuits 15, 16 may be arranged in the correspondingrelationship of 1:1 is adapted is illustrated as an example, it is notlimited to the configuration, but it is also able to adapt to such aconfiguration, etc. that arranges one by one the column signalprocessing circuits 15, 16 per a plurality of pixel columns (verticalsignal lines 24), to time-divide the column signal processing circuits15,16 between multiple pixel columns to use commonly them.

The horizontal driving circuits 17 may be constituted with shiftregisters or address decoders, etc. to select subsequently the columnsignal processing circuits 15 by outputting the horizontal scan pulsessequentially. The horizontal driving circuits 18 may be also, similarlyto the horizontal driving circuits 17, constituted with shift registersor address decoders, etc. to select subsequently the column signalprocessing circuits 16 by outputting the horizontal scan pulses in turn.

Further, though drawing is omitted, each of output stage of the columnsignal processing circuits 15, 16 has a horizontal selection switchwhich is connected with each of the horizontal signal lines 19, 20. Thehorizontal scan pulses φH1˜φHx output subsequently from the horizontaldriving circuits 17, 18 turn on in turn the horizontal selectionswitches connected to each output stage of the column signal processingcircuits 15, 16. These horizontal selection switches turn on in turn inresponse to the horizontal scan pulses and output in turn pixel signalsprocessed by the column signal processing circuits 15, 16 per each pixelcolumn to the horizontal lines 19, 20.

Output circuits 21, 22 carry out several signal processes for the unitpixel signal supplied in turn via the horizontal signal lines 19, 20from each of the column signal processing circuits 15, 16 and thenoutput the processed signals. As an example of specific signal processesof these output circuits 21, 22, there is a process buffering only, aprocess adjusting of a black level before the buffering, a processcorrecting differences between each column, a process amplifying signal,a process of color relation, or the like.

Circuit Configuration for Pixel

FIG. 2 is a diagram illustrating an example of circuit configuration ofthe unit pixel 11. The unit pixel 11 illustrated on FIG. 2 has a photodiode 41 for the photoelectric conversion device, a transmissiontransistor 42, a reset transistor 43, amplification transistor 44 andselection transistor 45.

Herein, as an example of the four transistors of transmission transistor42 to selection transistor 45, n typed-channel MOS transistor may beused. Merely, the above combination of a conductive type of thetransmission transistor 42, reset transistor 43, amplificationtransistor 44 and selection transistor 45 is only an example, and is notlimited to such combination.

Further, as illuminated in FIG. 2, the pixel driving wires 23 for theunit pixels 11 are arranged commonly for each pixel of the same pixelrows as pixel driving wires 23, for example, three driving wires of atransmission wire 23 a, a reset wire 23 b and a selection wire 23 c.Each one end of the transmission wire 23 a, reset wire 23 b andselection wire 23 c is connected in a unit of a pixel row to the outputend corresponding to each pixel row of the vertical driving circuit 14.

A photo diode 41 has an anode which is connected to a negative side, forexample, a ground and converts a sensed light into light electricalcharges (herein, photoelectron) of electrical charge amountcorresponding to the light amount (physical quantity). A cathode of thephoto diode 41 is connected electrically to a gate of the amplificationtransistor 44 with an intervention of the transmission transistor 42. Anode 46 connected electrically with the gate of this amplificationtransistor 44 is called to FD (floating diffusion) section.

The transmission transistor 42 is connected between the cathode of thephoto diode 41 and the FD section 46, and is turned on by applying atransmission pulse φTRF which a high level (e.g., Vdd level) isdisclosed to an active (hereinafter, “high active”) to its gate viatransmission wire 23 a to transmit the light electrical charge convertedin the photo diode 41 to the FD section 46.

The reset transistor 43 has a drain connected to a pixel power supplyVdd and a source connected to FD section 46, and is turned on byapplying a reset pulse φRST of a high active to its gate withintervention of the reset wire 23 b to reset FD section 46 by wastingthe electrical charges of the FD section 46 to the pixel power supplyVdd of the unit pixel before a transmission of signal from the photodiode 41 to the FD section 46.

The amplification transistor 44 has a gate connected to the FD section46 and a drain connected to the pixel power supply Vdd, and outputs theelectrical potential of the FD section 46 after resetting by the resettransistor 43 as a reset level, and further, outputs the electricalpotential of the FD section 46 after completion of the electrical chargetransmission of signal by the transmission transistor 42 as a signallevel.

The selection transistor 45 has the drain connected to the source of theamplification transistor 44 and the source connected to the verticalsignal line 24 and is turned on by applying the selection pulse φSEL ofthe high active to its gate with intervention of the selection wire 23 cto transmit the output signal from the amplification transistor 44 tothe vertical signal line 24 as a selected state of the unit pixel 11.

Further, the selection transistor 45 may be able to adapt aconfiguration of a circuit connected between the unit pixel power supplyVdd and the drain of the amplification transistor 44.

Further, the unit pixel 11 is not limited to the configuration of thefour transistors, and may be able to be circuit constitutions formedfrom three transistors compatible with the selection transistor 45 asthe amplification transistor 44 and, or other circuit constitutions.

Example Obtaining Signal Having Different Sensitivities from MultipleChannels

The CMOS image sensor 10 related to an embodiment according to the aboveconfiguration may obtain via multi-channels, for example, two channelsin the present embodiment, the signals having different sensitivitiesfrom each pixel 11 of the unit pixel array section 12 in order to get awide dynamic range.

The vertical driving circuit 14 carries out a shutter scan in anelectronic shutter scan channel and a reading-out scan by the twochannels, for each pixel 11 of the unit pixel array section 12 and isable to obtain signals having different sensitivities (to makedifferently signal sensitivities in two channels) by differing adetection time i.e., the exposure time for detecting a light amount as aphysical quantity by the pixel 11. The length of the exposure time(detection time) is adjusted by an interval of the reading-out scan ofthe two channels. The specific description thereof is given below.

In the reading-out scan, as illustrated on the left side of FIG. 3, twopixel rows are respectively scanned as read-out rows 1, 2 of twochannels, and each pixel signal from these 2 read-out rows 1, 2 areread-out to the vertical signal line 24. Further, the column signalprocessing circuits 15, 16 of the two channels are installedcorresponding to the reading-out scan of two channels.

By the vertical scan, as illustrated on the right side of FIG. 3, sincea time from a shutter row to a read-out row 1 that the read-out scan offirst turn is performed is an exposure time 1 and a time from theread-out row 1 to the read-out row 2 that the read-out scan of secondturn is performed is an exposure time 2, by setting differently theseconsecutive two exposure times (storage time) 1, 2, two signals havingdifferent sensitivities from the same pixel, that is, the lowsensitivity signal based on a short exposure time 1 and other being athe high sensitivity signal based on a long exposure time 2 areobtainable successively. The setting of the exposure times 1, 2 isprocessed by the control circuit 13.

By combining the two signals having different sensitivities, namely, alow sensitivity signal and a high sensitivity signal in a combingcircuit (not shown) in the later stage, the image signal having the widedynamic range is able to be obtained. The information of the highilluminance portion of the image signal obtained in this manner is ableto be obtained from the low sensitivity signal based on the shortexposure time 1, and the information of the low illuminance portion ofthe obtained image signal is able to be obtained from the highsensitivity signal based on the long exposure time 2. With regard tothis, the signal of the high sensitivity signal is referred to a lowsensitivity signal and the signal of the high sensitivity is referred toa low sensitivity signal.

Further, with regard to the shutter scan and the reading-out scan asdescribed above, it can be implemented by the following configuration.

In other words, as aforementioned, in the vertical driving circuit 14having the reading-out scan channel and the electronic shutter scanchannel (sweeping scan channel), the electronic shutter scan channel maybe constituted with the shift register for example, and outputs anelectronic shutter pulse from the shift register in a pixel row unitfrom the first row subsequently, whereby it is possible to carry out arolling shutter operation (or focal plane shutter operation) carryingout the shutter scan from the first row subsequently.

Meanwhile, the reading-out scan channel may be constituted with twoshift registers, by outputting the scan pulses 1, 2 which select readingout rows 1, 2 from these two shift registers subsequently, it ispossible to perform the reading-out scan of two channels. Further, thereading-out scan channel may be also constituted with a address decoder,by assigning address for each row 1, 2 by the corresponding addressdecoder, it is possible to perform the reading-out scan of two channels.

In this manner, by carrying out the shutter scan by the electronicshutter scan channel and the reading-out scan of two channels by thereading-out scan channel, signals of two channels having differentsensitivities are obtainable.

Specifically, as illustrated on the left side of FIG. 3, the shutter rowis first scanned and then two read-out rows 1, 2 are scanned. Forexample, a signal output from the each pixel of the read-out row 1 canbe read-out in column signal processing circuit 15 and an output signalfrom each pixel of the read-out row 2 can be read-out in the columnsignal processing circuit 16. The combination of the read-out rows 1, 2and the column signal processing circuits 15, 16 can be changed.

Which one of the column signal processing circuits 15, 16 reads out thesignal of which one row of the read-out rows 1, 2 is determined byoperation timings of each of the column signal processing circuits 15,16. Namely, if the column signal processing circuit 15 (16) operates bythe scan timing of the read-out row 1, each pixel signal of the read-outrow 1 is read-out by the column signal processing circuit 15 (16), andif the column signal processing circuit 16 (15) operates by the scantiming of the read-out row 2, each pixel signal of the read-out row 2 isread-out by the column signal processing circuit 16 (15).

In FIG. 3 right side, the transverse axis represents a time and ascanning profile. Here, the read-out row 1 is defined as the shortexposure time 1 and the read-out row 2 is defined as the long exposuretime 2, in order to promote understanding, as an example, the exposuretime 1 is defined as 2 row portion of time 2H (H is horizontal period)and the exposure time 2 is defined as 8 row portion of time 8H. Thus,the unit pixel sensitivity of the read-out row 1 is low and the unitpixel sensitivity of the read-out row 2 is higher as 4 times than theread-out row 1.

Configuration of Column Signal Processing Circuit

FIG. 4 is a block diagram illustrating an example of a column signalprocessing circuits 15, 16. Herein, for convenience of explain, all ofsignals in the column signal processing circuits 15, 16 are indicated indirection from left to right.

The column signal processing circuit 15 is able to be constituted with aCDS processing circuit 51, an AD conversion circuit 52 and a latchcircuit 53.

The CDS processing circuit 51 eliminates the unit pixel's intrinsicfixed-pattern noises from signal level (the high illuminance portion)corresponding to the light amount of the incident light, by takingdifferences between the reset levels and the signal levels asaforementioned which are supplied via a vertical signal line 24 from theunit pixels 11 constituting the unit pixel array section 12 and thencarrying out the CDS process. The AD conversion circuit 52 converts theanalog signal (the high illuminance portion) eliminated noises by theCDS processing circuit 51 on the basis of the control circuit 13. Thedigital circuit 53 stores the digital signal which is Ad-converted andoutput from the AD conversion circuit 52.

The column signal processing circuit 16 has basically the sameconfiguration as the column signal processing circuit 15. Specifically,the column signal processing circuit 16 is constituted with a CDSprocessing circuit 61, an AD conversion circuit 62 and a latch circuit63.

Namely, the CDS processing circuit 61 eliminates the unit pixel'sintrinsic fixed-pattern noises from a signal level (the low illuminanceportion) corresponding to the light amount of the incident light bycarrying out the CDS process to take a difference between the resetlevel and the signal level as aforementioned which is supplied via avertical signal line 24 from the unit pixel 11 constituting the unitpixel array section 12. The AD conversion circuit 62 converts the analogsignal (the high illuminance portion) in which a noise is eliminated inthe CDS processing circuit 61 on the basis of the control circuit 13.The digital circuit 63 stores the digital signal which is Ad-convertedand output from the AD conversion circuit 62.

Like this, a digital signal DH corresponding to the high illuminancesignal stored in the latch circuit 53 is read-out by the horizontal scanof the horizontal driving circuit 17 via the horizontal scan line 19,and a digital signal DL corresponding to the low illuminance signalstored in the latch circuit 63 is read-out by the horizontal scan of thehorizontal driving circuit 18 via the horizontal scan line 20.

In addition, the combining circuit 71 combines the digital signal DHcorresponding to the low illuminance signal read-out from the latchcircuit 53 and the digital signal DL corresponding to the lowilluminance signal read-out from the latch circuit 63 to output acombination signal D. Further, the combining circuit 71 is provided witha memory storing and holding signals corresponding to a plurality ofrows, and it is able to store and hold temporarily the signal from theread-out row 1, and thus, when the same pixel signal from the read-outrow 2 is output, it is able to combine each of signals.

In addition, in FIG. 4, though the output circuits 21, 22 are notilluminated, actually, as illuminated with reference with FIG. 1, theunit pixel signal from the column signal processing circuit 15 issupplied to the output circuit 21, and the unit pixel signal from thecolumn signal processing circuit 16 is supplied to the output circuit22. That is, the combining circuit 71 combines the digital signal DHoutput from the output circuit 21 and the digital signal DL output fromthe output circuit 22.

Combining of Low Illuminance Signal and High Illuminance Signal

Herein below, with reference to FIG. 5 and FIG. 6, there is givendisclosures of the process combining a digital signal DH correspondingto the high illuminance portion and a digital signal DL corresponding tothe low illuminance portion by the combining circuit 71.

In addition, hereinafter, the digital signal DH corresponding to thehigh illuminance signal and the digital signal DL corresponding to thelow illuminance signal are referred to a high illuminance signal DH anda low illuminance signal DL, respectively.

FIG. 5 illustrates a dynamic range of a low illuminance signal DL and ahigh illuminance signal DH for an incident light amount of the CMOSimage sensor 10.

Here, if a ratio (sensitivity ratio) of sensitivities of an analog ofthe low illuminance signal and the high illuminance signal, in otherwords, an analog output ratio of the unit pixel 11 per a unit lightamount is 4:1, the ratio of the light amount (light amount ratio) per 1mV of the low illuminance signal and the high illuminance signal isbecame 1:4, and in the low illuminance signal DL and the highilluminance signal DH per the quantized unit (1 LSB) of AD conversion, arelationship of the following formula (1) is established.

Low illuminance signal DL=high illuminance signal DH×4  (1)

At this time, the combining circuit 71 outputs the low illuminancesignal DL for the low illuminance portion on a screen as it is, as acombination signal D and amplifies the high illuminance signal DH forthe high illuminance portion on the image surface, 4 times and outputsthe signal as a combination signal D. Namely, the combining circuit 71outputs either the low illuminance portion DL or the high illuminanceportion DH, as the combination signal D, selectively. Thereby, it isable to expand the dynamic range.

However, actually, since a deviation is included in relation to theformula (1), it is not able to output a correct digital signal of lightamount near a border when selected either any one of the low illuminancesignal DL or the high illuminance signal DH.

Therein, the combining circuit 71 outputs a combining signal Drepresenting by the following formula (2) such that in case that therange of La and Lb illuminating on FIG. 5 is at low illuminance side, itis added (weighted average) to the low illuminance signal DL and in casethat the range of La and Lb is at high illuminance side, it is added tothe high illuminance signal DH.

Combining signal D=low illuminance signal DL×α+high illuminance signalDH×4×(1−α)  (2)

Further, in the formula (2), coefficient α is substituted by a valueindicating on FIG. 6. Namely, the coefficient α takes 1 in case that thelow illuminance signal DL is smaller than a value a corresponding to alight amount La and takes 0 in case that the low illuminance signal DLis larger than a value b corresponding to a light amount Lb. Also, Incase that the low illuminance signal DL is larger than the value acorresponding to the light amount La and is smaller than the value bcorresponding to the light amount Lb, the coefficient α changes from 1to 0 according to increasing of the low illuminance signal DL. Further,the value 4 in the formula (2) is a value by light amount ratio of thelow illuminance signal and the high illuminance signal per a quantizedunit.

Thereby, the combining circuit 71 outputs the low illuminance signal DL(in FIG. 5, solid line portion of low illuminance signal) as acombination signal D in case that the light amount is smaller than Laand outputs a value that is multiplied the high illuminance signal DH(in FIG. 5, solid line portion of the high illuminance signal) by 4folds as a combined signal in case that the light amount is larger thanLb, and further, outputs a combination signal D obtained by the weightedaverage value presented in the formula (2) above in case that the lightamount is larger than La and is smaller than Lb.

By above, the combining circuit 71 is able to output a correct digitalsignal in companying with expanding the dynamic range.

By the way, in case of raising the gain setting of CMOS image sensor 10related to the present embodiment, a process raising the analog gain iscarried out. Specifically, the control circuit 13 sets the quantizedunit (1 LSB) of the AD conversion by the AD conversion circuits 52, 62according to setting of the analog gain. Specifically, for example, inorder to get two fold of a gain of the digital signal output from thecombining circuit 71, in other words, the low illuminance signal DL andthe high illuminance signal DH output from the column signal processingcircuits 15, 16, the quantized unit of the AD conversion by the ADconversion circuits 52, 62 should be ½ fold.

Here, in FIG. 4, a signal (analog signal) from the unit pixel 11 of theunit pixel array 12 outputs 400 mV maximum and each input range of theAD conversion circuits 52, 62 is 0 to 500 mV. In case that the gainsetting of analog gain, as illuminated on FIG. 7, the low illuminancesignal and the high illuminance signal are AD-converted by maximumoutput (400 mV) of the unit pixel 11 together. However, in case that thegain setting of the analog gain is 2 fold, in order that the quantizedunit AD-converted becomes ½ fold, each input range of the AD conversioncircuits 52, 62 is relatively became 0 to 250 mV. Therefore, asillustrated on FIG. 7, the low illuminance signal and the highilluminance signal are AD-converted only by 250 mV of signal portion andthus the information corresponding to 250 to 400 mV of signal I portionis lost.

In this case, for example, with regard to the low illuminance signal ofFIG. 5, the information corresponding to the signal obtainable near thelight amount La among signals representing with the solid line portionoutput as it is as the combination signal D is discarded to be lost.Though this lost information may be obtained from the high illuminanceportion, since the S/N of the high illuminance portion is low than thelow illuminance portion, there is worry about that the S/N of image isbecame low.

Therein, the control circuit 13 determines the grayscale number of thedigital output of the AD conversion for the low illuminance portion bythe AD conversion circuit 62 according to the gain setting of the analoggain. Specifically, the control circuit 13 is capable of controlling toget bigger the grayscale number, namely, grayscale number, of digitaloutput of the AD conversion for the low illuminance portion by the ADconversion circuit 62 when raising the analog gain. Here, so called thegrayscale number is an AD-converted grayscale number multiplied by 2squares such that 10 bits are corresponding to 1024 and 12 bits arecorresponding to 4096, etc. In addition, according to a kind of the ADconversion circuit, it is able to carry out the AD conversion withgrayscale number of not 2 squares, but e.g. 3000 and the like.

Relationship of Analog Gain with Grayscale Number of AD Conversion forLow Illuminance Signal

Herein, with reference to FIG. 8 and FIG. 9, an explanation torelationship of the gain setting with the grayscale number of the ADconverted analog gain is given. FIG. 8 illustrates a relationship of ananalog gain with the grayscale number of the AD conversion for the lowilluminance signal and the high illuminance signal, FIG. 9 illustratesthe grayscale number of AD conversion, the input range, the quantizedunit (1 LSB) and the light amount ratio near 1 LSB of the lowilluminance signal and the high illuminance signal for the analog gain.

In addition, each of the AD conversion circuits 52, 62 is able toconvert a maximum 12 bits of the digital output and thus is able to varythe grayscale number (grayscale number).

Specifically, for example, in case that the AD conversion circuits 52,62 have a configuration comparing a reference voltage with an inputvoltage or is a delta sigma typed-AD conversion circuit, the grayscalenumber is able to be varied by either one of changing an operationfrequency of a counter or changing a time covering the AD conversion.Further, in case that the AD conversion circuits 52, 62 is a sequentialcompared-typed AD conversion circuit, the grayscale number is able to bevaried by a number of comparison. Further, in case that AD conversioncircuits 52, 62 is a flash typed-AD conversion circuit, the grayscalenumber is able to be varied by being an unnecessary comparator instandby state, and in case that AD conversion circuits 52, 62 is apipeline typed-AD conversion circuit, the grayscale number is able to bevaried by changing of the used stage number.

Furthermore, the AD conversion circuits 52, 62 are not limited to theabove configuration and are preferable to adapt a configuration having avariable grayscale number.

(1) A case of usual gain (gain setting is 1 fold) without any gainsetting

First, as illustrated on FIG. 8 upper side, the low illuminance signaland the high illuminance signal are AD-converted by the maximum output(for example, 400 mV) of the unit pixel 11 of the unit pixel arraysection 12 together. At this time, the digital output AD-converted bythe AD conversion circuit 62 for the low illuminance portion is regardedas maximum 10 bits and the digital output AD converted by the ADconversion circuit 52 for the high illuminance portion is became maximum12 bits by the control circuit 13.

In this case, as illustrated on FIG. 9, each input range of the ADconversion circuits 52, 62 is 0 to 500 mV, and the quantized unit of theAD conversion by the AD conversion circuits 52, 62 is becameapproximately 0.13 mV and 0.5 mV respectively. Further, if thesensitivity ratio of the low illuminance signal and the high illuminancesignal, that is, the analog output ratio of the unit pixel 11 per a unitlight amount is 16:1, the light amount ratio per 1 mV of the lowilluminance signal and the high illuminance signal is became 1:16 andthus the light amount ratio of the quantized unit (1 LSB) of the lowilluminance signal and the high illuminance signal is became 1:4 (inFIG. 9, a value representing a size of light amount of the highilluminance portion when the size of light amount of the low illuminanceportion per quantized unit is 1 is 4. Also, if the quantized unit (1LSB) of the low illuminance portion is a reference, the input range ofthe AD conversion circuit 52 for the high illuminance portion is became14 bits part. Thus, the combination signal D is became 14 bits.

(2) A Case in which Gain Set is Two Fold

In this case, according to the control circuit 13, the quantized unit ofthe AD conversion by the AD conversion circuits 52, 62 is ½ fold inrelation to a usual gain value. At this time, according to the controlcircuit 13, as illustrated on FIG. 8 mid-stage, the AD-converted digitaloutput for the high illuminance portion by the AD conversion circuit 62is regarded as maximum 11 bits and the AD-converted digital output forthe low illuminance portion by the conversion circuit 52 is regarded asmaximum 12 bits. Thereby, the high illuminance portion is AD-convertedonly by signal portion of 250 mV, and thus the information correspondingto the signal portion of 250 to 400 mV is lost, but the low illuminanceportion is AD-converted by the maximum output of the unit pixel 11.

Namely, as illustrated on FIG. 9, if each input range of the ADconversion circuits 52, 62 is became 250 mV and 500 mV respectively, thequantized unit of the AD conversion by the AD conversion circuits 52, 62are became 0.063 and 0.25 mV respectively. Also, if the sensitivityratio of the low illuminance signal and the high illuminance signal is16:1, the light amount ratio per 1 mV of the low illuminance signal andthe high illuminance signal is became 1:16 and thus the light amountratio per a quantized unit (1 LSB) of the low illuminance signal and thehigh illuminance signal is became 1:4 as in case of the usual gain.Also, if the quantized unit (1 LSB) of the low illuminance portion is areference, the input range of the AD conversion circuit 52 for the highilluminance portion is became 14 bits portion. Thus, the combinationsignal D is became 14 bits.

(3) A Case in which Gain Set is 4 Fold

In this case, according to the control circuit 13, the quantized unit ofthe AD conversion by the AD conversion circuits 52, 62 is ½ fold inrelation to a case the gain value is two fold. At this time, accordingto the control circuit 13, as illustrated on the lower side of FIG. 8,the AD-converted digital output for the low illuminance portion by theconversion circuit 62 is regarded as maximum 12 bits and theAD-converted digital output for the high illuminance portion by theconversion circuit 52 is became maximum 12 bits. Thereby, the highilluminance portion is AD-converted only by signal portion of 125 mV,and thus the information corresponding to the signal portion of 125 to400 mV is lost, but the low illuminance portion is AD-converted by themaximum output of the unit pixel 11.

Namely, as illustrated on FIG. 9, if each input range of the ADconversion circuits 52, 62 is became 125 mV and 500 mV respectively, thequantized unit of the AD conversion by the AD conversion circuits 52, 62are became 0.031 and 0.13 mV respectively. Also, if the sensitivityratio of the low illuminance signal and the high illuminance signal is16:1, the light amount ratio per 1 mV of the low illuminance signal andthe high illuminance signal is became 1:16 and thus the light amountratio per the quantized unit (1 LSB) of the low illuminance signal andthe high illuminance signal is became 1:4 as in case of the usual gain.Also, if the quantized (1 LSB) of the low illuminance portion is areference, the input range of the AD conversion circuit 52 for the highilluminance portion is became 14 bits portion. Thus, the combinationsignal D is became 14 bits.

(4) A Case in which Gain Set is 8 Fold

In this case, according to the control circuit 13, the quantized unit ofthe AD conversion by the AD conversion circuits 52, 62 is ½ fold inrelation to a case the gain value is 4 fold. Here, the AD conversioncircuits 52, 62 AD-converts the digital output by a maximum 12 bits andtherefore, according to the control circuit 13, the AD-converted digitaloutput for the low illuminance portion by the conversion circuit 62 andthe AD-converted digital output for the high illuminance portion by theconversion circuit 52 are regarded as maximum 12 bits. Thereby, the highilluminance portion is AD-converted only by signal portion of 63 mV, andthus the information corresponding to the signal portion of 63 to 400 mVis lost, and further, the low illuminance portion is AD-converted onlyby signal portion of 250 mV, and thus the information corresponding tothe signal portion of 250 to 400 mV is lost.

Namely, as illustrated on FIG. 9, if each input range of the ADconversion circuits 52, 62 is became 63 mV and 250 mV respectively, thequantized unit of the AD conversion by the AD conversion circuits 52, 62are became 0.016 mV and 0.063 mV respectively. Also, if the sensitivityratio of the low illuminance signal and the high illuminance signal is16:1, the light amount ratio per 1 mV of the low illuminance signal andthe high illuminance signal is became 1:16 and thus the light amountratio per quantized unit (1 LSB) of the low illuminance signal and thehigh illuminance signal is became 1:4 as in case of the usual gain.Also, if the quantized unit (1 LSB) of the low illuminance portion is areference, the input range of the AD conversion circuit 52 for the highilluminance portion is became 14 bits portion. Thus, the combinationsignal D is became 14 bits.

(5) A Case in which Gain Set is 16 Fold

In this case, according to the control circuit 13, the quantized unit ofthe AD conversion by the AD conversion circuits 52, 62 is became ½ foldin relation to a value of the case the gain setting is 8 fold. Here,since AD conversion circuits 52, 62 AD-converts the digital output by amaximum 12 bits, likewise as the case the gain setting is 8 fold,according to the control circuit 13, the digital output AD-converted forthe low illuminance signal by the AD conversion circuit 62 and thedigital output AD-converted for the high illuminance signal by the ADconversion circuit 52 are all regarded as maximum 12 bits. Thereby, thehigh illuminance signal is AD-converted only by signal of 31 mV, andthus the information corresponding to the signal of 31 to 400 mV islost, and further, the low illuminance signal is AD-converted only bysignal of 125 mV, and thus the information corresponding to the signalof 125 to 400 mV is lost.

Namely, as illustrated on FIG. 9, if each input range of the ADconversion circuits 52, 62 is became 31 mV and 125 mV respectively, thequantized unit of the AD conversion by the AD conversion circuits 52, 62are became approximately 0.008 mV and 0.031 mV respectively. Also, ifthe sensitivity ratio of the low illuminance signal and the highilluminance signal is 16:1, the light amount ratio per 1 mV of the lowilluminance signal and the high illuminance signal is became 1:16 andthus the light amount ratio per quantized unit (1 LSB) of the lowilluminance signal and the high illuminance signal is became 1:4 as incase of the usual gain. Also, if the quantized (1 LSB) of the lowilluminance signal regards as a reference, the input range of the ADconversion circuit 52 for the high illuminance signal is became 14 bitspart. Thus, the combination signal D is became 14 bits.

As above, in the case of usual gain, if the control circuit 13 iscapable of controlling to determine the grayscale number of the ADconversion for the low illuminance portion by the AD conversion circuit62 smaller bits number than the grayscale number of the AD conversionfor the high illuminance portion by the AD conversion circuit 52, and iscapable of controlling to be more greater (increasing the bits number)the grayscale number of the AD conversion for the low illuminanceportion by the AD conversion circuit 62 whenever the gain setting israise, there is no matter that even though the quantized is small andthus it is able to maintain the input range of the AD conversion 62 asthe case of the usual gain.

Also, since the AD conversion circuit 62 AD-converts the digital outputby maximum 12 bits, the above exemplary embodiment is unable to increasethe grayscale number (increasing of bits number) of the AD conversionfor the low illuminance portion by the AD conversion circuit 62 in thecase that the gain setting is 8 fold. In this case, the informationcorresponding to the low illuminance portion for which is notAD-converted is lost.

Like this, in the embodiment of FIG. 9, the input range of the ADconversion circuit 62 is able to be maintained by 4 fold of gain settingas in the case of usual gain.

Here, if the AD conversion circuit 62 is able to AD-convert the ADconversion of the digital output by maximum 14 bits, it is able tomaintain the input range of the AD conversion circuit 62 by more highergain setting as in the case of usual gain.

Namely, as illustrated on FIG. 10, in a case the gain setting is 8 fold,according to the control circuit 13, the quantized unit of the ADconversion by the AD conversion circuits 52, 62 is ½ fold in relation tothe case the gain value is 4 fold. At this time, according to thecontrol circuit 13, the digital output of the AD conversion for the lowilluminance portion by the AD conversion circuit 62 is became maximum 13bits, and the digital output of the AD conversion for the highilluminance portion by the AD conversion circuit 52 is became maximum 12bits. Thereby, the high illuminance portion is AD-converted only bysignal portion of 63 mV, and thus the information corresponding to thesignal portion of 63 to 400 mV is lost, but the low illuminance portionis AD-converted by the maximum output of the unit pixel 11.

Also, in a case the gain setting is 16 fold, according to the controlcircuit 13, the quantized unit of the AD conversion by the AD conversioncircuits 52, 62 is ½ fold in relation to a case the gain value is 8fold. At this time, according to the control circuit 13, the digitaloutput of the AD conversion for the low illuminance portion by the ADconversion circuit 62 is became maximum 14 bits, and the digital outputof the AD conversion for the high illuminance portion by the ADconversion circuit 52 is became maximum 12 bits. Thereby, the highilluminance portion is AD-converted only by signal portion of 31 mV, andthus the information corresponding to the signal portion of 31 to 400 mVis lost, but the low illuminance portion is AD-converted by the maximumoutput of the unit pixel 11.

Like this, in the embodiment of FIG. 10, the input range of the ADconversion circuit 62 is able to be maintained by 16 fold of gainsetting as in the case of usual gain.

Further, in the embodiment of FIG. 10, if the sensitivity ratio is 16fold and the gain setting is 16 fold, the 500 mV of the low illuminanceportion and 31 mV of the high illuminance portion correspond to asubstantially same light amount and therefore, the high illuminanceportion is not necessary. In this condition as in FIG. 11, it referspreferably that the high illuminance portion is “non-use”

Further, in the above description, though it is assume that each of theAD conversion circuits 52, 62 is to vary the output bits number(grayscale number) of the AD conversion, it may be preferable that theoutput bits number of the AD conversion circuit 52 is to be fixed to 12bits and only the output bits number of the AD conversion circuit 62 isto be varied.

Further, in the above description, the reason fixing the grayscalenumber of the high illuminance portion to an certain value not byvariable gain is because the bits number of the combination signal D isfixed to a predetermined value of for example 14, etc. By this, in thesystem of the followed stage, it is able to process the general 14 bitsof signal without corresponding of the configuration adopted the presentdisclosure. In the system which is preferable even that the bits numberof the combination signal D is not fixed, though the combination signalD is changed by raising the gain and at the same time increasing thegrayscale of the high illuminance portion, it is able to obtain theinformation of the most big as possible by processing the signal withreference to the information by a specific mechanism.

Signal Output Process

Next, With reference to FIG. 12, it is given a disclosure of a signaloutput process which combines the low illuminance signal and the highilluminance signal from the pixel array section 12 to output thecombined signal as a digital signal in the CMOS image sensor 10.

In step S11, the column signal processing circuit 15 AD-converts thehigh illuminance signal from the unit pixel array 12.

Specifically, in the column signal processing circuit 15, the CDSprocessing circuit 51 carries out the CDS process for a signal (the highilluminance portion) of pixel 11 from the unit pixel array section 12and supplies the processed signal to AD conversion circuit 52. The ADconversion circuit 52 AD-converts the analog signal of the highilluminance signal from the CDS processing circuit 51 based on thecontrol of a control circuit 13. Here, in case that the gain setting ofthe analog gain is instructed, the control circuit 13 sets the quantizedunit of the AD conversion by the AD converting circuit 52 in accordingto a gain setting of the instructed analog gain. The digital the highilluminance signal DH AD-converted by the AD conversion circuit 52 isstored in a latch circuit 53.

In step S12, the column signal processing circuit 16 carries out the ADconversion process for the low illuminance portion from the unit pixelarray 12. Details of the AD conversion process for the low illuminanceportion will be described referring to FIG. 13, but the digital lowilluminance portion DL obtained by the result of the low illuminanceportion AD converting process is stored in the latch circuit 63.

In step S13, the combining circuit 71 combines the low illuminanceportion DH stored in the latch circuit 53 and the low illuminanceportion DL stored in the latch circuit 63 to output as the combinationsignal D on the basis of the above formula 2.

AD Conversion Process of Low Illuminance Signal

Next, referring to FIG. 13, details of AD conversion process of the lowilluminance portion carried out in the step S12 of a flowchart of FIG.12 is disclosed.

In step S31, the control circuit 13 determines whether or not thegain-up is instructed, that is, whether or not an instruction of raisingthe gain setting of the analog gain exists.

In step S31, if it was determined that the gain-up is instructed, theprocess goes to step S32, and the control circuit 13 is capable ofcontrolling to determine the grayscale number of the AD conversion bythe AD conversion circuit 62 according to the instructed gain setting.For example, when an instruction of raising the gain setting to two foldexists, in the embodiment of FIG. 9, the grayscale number of the ADconversion by the AD conversion circuit 62 is determined to 11 bits.

In step S33, the AD conversion circuit 62 AD-converts the determinedgrayscale number and the low illuminance portion by the control circuit13.

Specifically, the CDS processing circuit 61 carries out the CDS processfor the signal (the low illuminance portion) from the unit pixel 11 ofthe unit pixel array section 12 to supply to the AD conversion circuit62. The AD conversion circuit 62 AD-converts the analog the lowilluminance portion from the CDS processing circuit 61 on the basis ofthe quantized unit of the AD conversion that is set by the controlcircuit 13 and the grayscale number of the AD conversion determined bythe control circuit 13 in response to the gain setting of the analoggain. The digital low illuminance portion DL AD-converted by the ADconversion circuit 62 is stored in the latch circuit 63.

While, in the step S31, when determined that an instruction raising thegain does not exist, the process goes to step S34.

In the S34, the AD conversion circuit 62 AD-converts the low illuminanceportion of analog signal from the CDS processing circuit 61 with thepredetermined grayscale number determined already by the control circuit13. The digital low illuminance portion DL AD-converted by the ADconversion circuit 62 is stored in the latch circuit 63.

By the above process, when raising-up the gain setting, by increasing(increasing bits number) the grayscale number of the AD conversion forthe low illuminance portion by the AD conversion circuit 62, even thoughthe quantized unit becomes to small, it is able to maintain the inputrange of the AD conversion circuit 62 as same as before raising of thegain setting. Thus, in case of obtaining multiple signals havingdifferent sensitivities and expanding the dynamic range, for example, inthe low illuminance portion of FIG. 5, it is able to prevent the loss ofinformation corresponding to signal obtained near the light amount Laamong the signal representing with solid line portion output as it is asthe combination signal D and thus it is able to obtain a high S/N ofimage.

Also, the AD conversion circuit 62 is able to carry out the ADconversion with a high output it number (grayscale number). However, ifthe gain setting is low, since it is capable of controlling (driving) toget down the output bits number and carry out AD conversion, even whensetting to the low gain, it is able to reduce the power to be consumedby the AD conversion circuit 62.

Further, as disclosed referring to FIG. 9, even though the gain settingis changed, the light amount ratio per the quantized unit of the lowilluminance signal and the high illuminance signal is not changed with1:4. Thus, since it is not necessary to change the formula of thecombination signal D representing with the formula (2), it is able toavoid the increasing of an operation load in the combining circuit 71.

In addition, on the above, the technology has been disclosed inconnection with an embodiment adapted the present disclosure to aconfiguration such that varies an exposure time to obtain a plurality ofsignals having different sensitivities and as the result, expand thedynamic range. However, it is desirable to adapt the present disclosureto other configurations obtainable a plurality of signal having adifferent sensitivity. Namely, for example, it is also desirable toadapt the present disclosure to a configuration such that obtains aplurality of signals having different sensitivities by a capacitancedifference of portions read-out in a pixel and then, expand the dynamicrange.

Further, in the above, though the column signal processing circuit hasbeen provided with 2 pieces in a column (on the upper and lower portionof pixel array section 12), it is also desirable to provide with onlyone piece in a column and to process each pixel signal of a plurality ofrows by one column signal processing circuit.

In addition, the present disclosure is not limited to an adaption to thesolid-state imaging device. Namely, the present disclosure is able toadapt to a whole electronic apparatus using a solid-state imaging devicein an image read-in section (photoelectric conversion section) such as adigital camera or video camera, etc, a potable terminal device having animage sensing function, or a copy machine using a solid-state imagingdevice in an image read-out section, or the like. The solid-stateimaging device may be an integrated form into one-chip, or a module typehaving an image sensing function in which an image sensing section andsignal processing section, or optical system are arranged and packagedinto one form.

Configuration Example of Electronic Appliance Adapted to PresentDisclosure

FIG. 14 is a block diagram illustrating an example of the image sensingdevice in electronic appliances provided with the present disclosure.

The imaging device 300 of FIG. 14 may be provided with an opticalsection 301 constituted by a lens group, etc., a solid-state imagingdevice (image sensing device) 302 to which each of the configuration forthe unit pixel 11 disclosed above is adapted, and a DSP (Digital SignalProcessor) circuit 303 as of a camera signal processing circuit.Further, the imaging device 300 may be also provided with a frame memory304, a display section 305, a recording section 306, a control section307, a power supply section 308 and a CPU 309. The DSP circuit 303,frame memory 304, display section 305, recording section 306, controlsection 307, power supply section 308 and CPU 309 are connected via abus line 310 each other.

The optical section 301 receives an incident light (image light) from asubject and forms an image on an image sensing surface of thesolid-state imaging device 302. The solid-state imaging device 302converts the incident light amount formed on the sensing surface into anelectric signal of the unit pixel unit by the optical section 301 andoutputs the signal as a pixel signal. It is able to use the solid-stateimaging device realizing the expansion of the solid-state imagingdevice, that is, a dynamic range of the CMOS image sensor 10, etc.related to the forms of embodiment disclosed above as the solid-stateimaging device 302.

The display section 305 may be formed from, for example, a paneltyped-display unit of a liquid crystal panel or an organic EL (ElectroLuminescence) panel, for example, to display a dynamic image or a stillimage which is sensed by the solid-state imaging device 302. Therecording section 306 records a dynamic image or a still image sensed bythe solid-state imaging device 302 on a recoding medium such as a videotape, DVD (Digital Versatile Disk), or the like.

The control section 307 issues operational commands for carrying out avarious functions of the imaging device 300 under a control of user. Thepower supply section 308 supplies properly various kinds of powersources as power source for driving the DSP circuit 303, frame memory304, display 305, recording section 306 and control section 307 toportions which the power supply is desired to. The CPU 309 controls thewhole operation of the imaging device 300.

In addition, in the imaging device 300, the combining circuit 71illustrated on FIG. 4 may be preferably included at the output side ofthe solid-state imaging device 302, and the DSP circuit 303 maypreferably carry out an operation in the combining circuit 71. It ispreferable that the solid-state imaging device 302 and the DSP circuit303 may be integrated into one piece of the solid-state imaging deviceand the DSP circuit 303 converts AD conversion of the low illuminancesignal and the high illuminance signal to carry out the operation of thecombination signal.

Here, referring to a flowchart of FIG. 15, it is given a disclosure of again setting process in the imaging device 300. The gain setting processof FIG. 15 processes a case that an image sensing mode is set anauto-image sensing mode in the imaging device 300, and the like, forexample.

In step S51, the DSP circuit 303 determines by the solid-state imagingdevice 302, whether or not a luminance of the sensed image issufficient. Specifically, DSP circuit 303 determines whether or not theluminance value of the unit pixel signal from the solid-state imagingdevice 302 is greater than a predetermined value.

In Step S51, if determined that the luminance value is not sufficient,in step S52, the DSP circuit 303 instructs the gain-up to thesolid-state imaging device 302. Specifically, the DSP circuit 303instructs raising the gain setting of analog gain to the control circuit(e.g. corresponding to the control circuit 13 of CMOS image sensor 10)of the solid-state imaging device 302. Thereby, the solid-state imagingdevice 302 is able to output the gained-up digital signal (pixelsignal).

In a while, in step S51, if determined that the luminance is sufficient,the process is ended.

By carrying out the above process at a predetermined interval, even whenbeing in the dark place, it is able to display or record imagesbrightly.

Further, as in the above description, by using the CMOS image sensor 10related to the aforementioned embodiments as the solid-state imagingdevice 302, it is able to expand the dynamic range as well as to securea high S/N. Thus, it is capable to implement a high quality of thesensing image even for the imaging device 300 of the video camera, adigital camera, and camera module, etc. for mobile apparatus such as acell phone.

Further, in the above embodiment, there is disclosed of an exemplaryembodiment adapted to the CMOS image sensor which the unit pixels fordetecting the signal electrical charge corresponding to the light amountof the visible light as a physical amount which is arranged in the shapeof rows and columns. However, the present disclosure is not limited tothe adaption to the CMOS image sensor, but may be adapted to a whole ofthe column typed-solid-state imaging device in which the columnprocessing section is arranged for each pixel row of the unit pixelarray.

Further, the present disclosure is not limited to an adaption to thesolid-state imaging device detecting the distribution of the incidentlight amount of a visible light and image-sensing as a image, but may beadapted to a whole of the solid-state imaging device (physical amountdistribution sensing apparatus) such as a solid-state imaging devicesensing a distribution of incident amount of an infrared ray, X ray, orparticle, or the like as an image, or a finger-print detecting sensorchanging a distribution of other physical amount of a pressure or anelectrostatic capacity, etc. in a wide meaning into an electric signaland integrating in time to sense the image.

In addition, in the present specification, though the step disclosed onthe flow chart is according to the sequence as disclosed and isprocessed in time-series, it may be processed not in time-series, but inparallel or in a desired timing when called, or the like.

The present disclosure contains subject matter related to that disclosedin Japanese Priority Patent Application JP 2011-084904 filed in theJapan Patent Office on Apr. 6, 2011, the entire contents of which arehereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1. A solid-state imaging device comprising: a pixel array section thatpixels which detect a physical quantities are arranged in two dimensionsof matrix; an AD converting section that performs AD (Analog-Digital)conversion for a plurality of channels of analog pixel signals which areread-out from the pixel array section; and a control section that setsquantized units AD-converted by the AD conversion section according to again setting of the unit pixel signal, wherein the control sectiondetermines the grayscale number of digital outputs AD-converted for atleast one channel of the unit pixel signals according to the gainsetting of the pixel signal.
 2. The solid-state imaging device accordingto claim 1, wherein when raising the gain of the unit pixel signal, thecontrol section controls the quantized unit AD-converted by the ADconversion section to be small and the grayscale number of the digitaloutput AD-converted for the pixel signals of at least one channel to belarge.
 3. The solid-state imaging device according to claim 2, whereinthe AD conversion section performs AD conversion for pixel signals,which have different sensitivities from each other, of the plurality ofchannels, and when raising the gain of the unit pixel signal, thecontrol section controls the quantized unit AD-converted by the ADconversion section to be small and the grayscale number of the digitaloutput AD-converted for the unit pixel signals, of which the sensitivityis high, of at least one channel to be large.
 4. The solid-state imagingdevice according to claim 3, wherein when raising the gain of the unitpixel signal, the control section controls the grayscale number of thedigital output AD-converted for the unit pixel signal, of which thesensitivity is low, of at least one channel not to change.
 5. Thesolid-state imaging device according to claim 3, wherein before raisingthe gain of the unit pixel signal, the control section controls thegrayscale number of the digital output AD-converted for the unit pixelsignal, of which the sensitivity is high, of at least one channel to besmaller than the grayscale number of the digital output AD-converted forthe unit pixel signals, of which the sensitivity is low, of at least onechannel.
 6. The solid-state imaging device according to claim 3, whereinthe AD conversion section performs AD conversion for pixel signals,which have different sensitivities from each other, of the plurality ofchannels by setting differently a detecting time for detecting thephysical amount by the pixel.
 7. A method of driving a solid-stateimaging device including a pixel array section in which pixels fordetecting a physical quantities are arranged in two dimensions ofmatrix, an AD converting section that performs AD (Analog-Digital)conversion for a plurality of channels of analog pixel signals which areread-out from the pixel array section, and a control section that setsquantized units AD-converted by the AD conversion section according to again setting of the unit pixel signal, wherein the control sectiondetermines grayscale numbers of digital outputs AD-converted for atleast one channel of the unit pixel signals according to the gainsetting of the pixel signal, the method comprising: determining agrayscale number of the digital output AD-converted for the unit pixelsignal of at least one channel according to the gain setting of thepixel signal.
 8. An electronic apparatus which is provided with asolid-state imaging device, wherein the solid-state imaging devicecomprises: a pixel array section for arranging pixels detecting physicalquantities in two dimensions of matrix; an AD converting section forprocessing AD (Analog-Digital) conversion for a plurality of channels ofanalog pixel signals which are read-out from the unit pixel arraysection; and a control section for setting quantized units AD-convertedby the AD conversion section according to a gain setting of the unitpixel signal, wherein the control section determines grayscale numbersof digital outputs AD-converted for at least one channel of the unitpixel signals according to the gain setting of the pixel signal.